1. Field of the Invention
The present invention relates to a small semiconductor device such as a device with a wafer level chip size package, and to the fabrication of this type of semiconductor device, more particularly to the fabrication of electrodes on the surface of the package and their interconnections to pads on the semiconductor device within the package.
2. Description of the Related Art
With the recent rising demand for smaller, slimmer semiconductor integrated circuits, wafer level chip size packages have become prevalent, especially for thin semiconductor devices. A wafer level chip size package (WCSP) is simply a protective layer with a grid of hemispherical bump electrodes, formed on a semiconductor integrated circuit in the wafer processing stage before the wafer is diced into individual integrated circuit chips. WCSP semiconductor devices as thin as three-tenths of a millimeter (0.3 mm) have been developed.
In a conventional semiconductor device of the WCSP type, integrated circuits formed on the front major surface of the wafer are covered by a dielectric layer on which there are electrode pads electrically connected to the circuitry below. An interlayer dielectric film is then deposited, holes extending to the electrode pads are formed in this film, a layer of metal is deposited, filling the holes, and a conductive pattern of redistribution wiring is formed, extending from the holes to the grid sites where bump electrodes will be placed. Posts about one hundred micrometers (100 μm) high are created at these sites by coating the wafer with a layer of photoresist, forming holes in the photoresist layer, filling the holes with metal, and then removing the photoresist. The surface of the wafer is then sealed in a layer of resin injected in liquid form, after which the surface is polished to expose the posts, and hemispherical bumps are formed on the exposed ends of the posts. After this the wafer is diced into separate semiconductor devices. (See, for example, Japanese Patent Application Publication No. 2003-60120).
A problem with this process is that even after polishing, the resin layer is nearly as thick (e.g., 90 μm thick) as the original height of the posts, and takes up much of the total thickness (e.g., 30%) of the semiconductor device.
It is also known art to form bump electrodes without forming posts. (See, for example, Japanese Patent Application Publication No. H11-195665 and U.S. Pat. No. 6,621,164.)